Compressed Sensing Receivers: Theory, Design, and Performance Limits

Citation

Yoo, Juhwan (2012) Compressed Sensing Receivers: Theory, Design, and Performance Limits. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/Y3FA-VB87. https://resolver.caltech.edu/CaltechTHESIS:06122012-144158047

Abstract

The past 50 years have seen tremendous developments in electronics due to the rise and rapid development of IC-fabrication technology [1]. In addition to the production of cheap and abundant computing resources, another area of rapid advancement has been wireless technologies. While the central focus of wireless research has been mobile communication, an area of increasing importance concerns the development of sensing/spectral applications over bandwidths exceeding multiple GHz. Such systems have many applications ranging from scientific to military. Although some solutions exist, their large size, weight, and power make more-efficient solutions desirable.

At present, one of the principal bottlenecks in designing such systems is the power consumption of the back-end ADCs at the required digitization rate. ADCs are a dominant source of power consumption; it is also often the case that ADC block specifications are used to determine parameters for the rest of the signal chain, such as the RF front-end and the DSP-core which processes the digitized samples [2]. Historically, increases in system bandwidth have come from developing ADCs with superior performance.

In contrast to improving ADC performance, this work presents a system-level approach with the goal of minimizing the required digitization rate for observation of a given effective instantaneous bandwidth (EIBW). The approach was inspired by the field of compressed sensing [3–5]. Loosely stated, CS asserts that samples which represent random projections can be used to recover sparse and/or compressible signals with what was previously thought to be insufficient information. The primary contributions of this thesis include: the establishment of physical feasibility of CS-based receivers through implementation of the first fully-integrated high speed CS-based front-end known as the random-modulation pre-integrator (RMPI) [6–9], and the development of a principled design methodology based on a rigorous analytical and empirical feasibility study of the system.

The 8-channel RMPI was implemented in 90 nm CMOS and was validated by physical measurements of the fabricated chip. The implemented RMPI achieves an EIBW of 2 GHz, with > 54 dB of dynamic range. Most notably, the aggregate digitization rate is fs = 320 Msps, 12.5× lower than the Nyquist rate.

Thesis Files