Published August 25, 2003
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An Architecture for Asynchronous FPGAs
Abstract
We present an architecture for a quasi delay-insensitive asynchronous field-programmable gate array. The logic cell is a complete asynchronous pipeline stage and the interconnects are entirely delay insensitive, eliminating all timing issues from the place-and-route procedure.
Attached Files
Submitted - afpga-030808.ps
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Additional details
- Eprint ID
- 27068
- Resolver ID
- CaltechCSTR:2003.006
- Created
-
2003-08-25Created from EPrint's datestamp field
- Updated
-
2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports