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Published June 25, 2003 | Submitted
Report Open

An Asynchronous Register Bypass Transformation

Abstract

A register specification typically states that in each cycle there is a possible read followed by a possible write; the sequence is strict. A register core with a separate read and write port is more efficient, because it can read and write to different locations simultaneously, and hence in one cycle. In the Caltech MiniMIPS processor, a control structure was added to such a register core, so that it implements the desired specification.

Additional Information

© 2003 California Institute of Technology.

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Submitted - bypass.pdf

Submitted - bypass.ps

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Created:
August 22, 2023
Modified:
October 24, 2023