Published June 25, 2003
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An Asynchronous Register Bypass Transformation
- Creators
- Papadantonakis, Karl
Abstract
A register specification typically states that in each cycle there is a possible read followed by a possible write; the sequence is strict. A register core with a separate read and write port is more efficient, because it can read and write to different locations simultaneously, and hence in one cycle. In the Caltech MiniMIPS processor, a control structure was added to such a register core, so that it implements the desired specification.
Additional Information
© 2003 California Institute of Technology.Attached Files
Submitted - bypass.pdf
Submitted - bypass.ps
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bypass.pdf
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Additional details
- Eprint ID
- 27067
- Resolver ID
- CaltechCSTR:2003.005
- Created
-
2003-06-25Created from EPrint's datestamp field
- Updated
-
2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports