Published January 1, 2001
| Submitted
Technical Report
Open
Global and local properties of asynchronous circuits optimized for energy efficiency
- Creators
- Pénzes, Paul I.
- Martin, Alain J.
Chicago
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Abstract
In this paper we explore global and local properties of asynchronous circuits sized for the energy efficiency metric Et^2. We develop a theory that enables an abstract view on transistor sizing. These results allow us to accurately estimate circuit performance and compare circuit design choices at logic gate level without going through the costly sizing process. We estimate that the improvement in energy efficiency due to sizing is 2 to 3.5 times when compared to a design optimized for speed.
Additional Information
© 2001 California Institute of Technology. We wish to thank the members of the Asynchronous VLSI Group at Caltech for many stimulating discussions: Mika Nyström Catherine Wong and Karl Papadantonakis and José Tierno from IBM TJ Watson Research Center. The research described in this paper was sponsored by the Defense Advanced Research Projects Agency and monitored by the Air Force under contract F29601-00-K-0184.Attached Files
Submitted - CSTR2001.pdf
Submitted - paper_new.ps
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Additional details
- Eprint ID
- 26925
- Resolver ID
- CaltechCSTR:2002.002
- Defense Advanced Research Projects Agency (DARPA)
- Air Force Office of Scientific Research (AFOSR)
- F29601-00-K-0184
- Created
-
2002-04-11Created from EPrint's datestamp field
- Updated
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2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports