Published May 1998
| Submitted
Technical Report
Open
The design of high performance asynchronous circuits for the Caltech MiniMIPS processor
- Creators
- Pénzes, Paul I.
Chicago
An error occurred while generating the citation.
Abstract
The purpose of this report is to describe the design and implementation of an asynchronous Fetch unit used in the high-performance Caltech MiniMIPS microprocesors. The Caltech MiniMIPS microprocesors was designed based on the Martin synthesis techniques. The main goals of this project were to investigate new architectural issues in asyncronous processor design and to develop new techniques and tools that can meet high throughput requirements.
Additional Information
© 1998 California Institute of Technology. Submitted May, 1998. I wish to thank the members of Asynchronous VLSI Group at Caltech for many stimulating discussions: Andrew Lines, Rajit Manohar, Mika Nyström, Robert Southworth and Catherine Wong. Special thanks to Rajit Mahonarfor designing and laying out the branch adder and for the very instructive discussion we had, to Uri Cummings for designing and laying out the incrementer and to Andrew Lines for the vehement debated we had ove the fetch. Last, but not least, thanks to Alain Marting for being my advisor and teaching me asynchronous VLSI.Attached Files
Submitted - msthesis.pdf
Submitted - msthesis.ps
Files
msthesis.pdf
Files
(1.1 MB)
| Name | Size | Download all |
|---|---|---|
|
md5:f497c99637567b8b162d37ac83d516e7
|
649.6 kB | Download |
|
md5:e86e29d6a011fd601dd1c2a4e477de79
|
495.3 kB | Preview Download |
Additional details
- Eprint ID
- 26924
- Resolver ID
- CaltechCSTR:2002.001
- Created
-
2002-04-11Created from EPrint's datestamp field
- Updated
-
2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports