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Published September 25, 2002 | Submitted
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Speed and Energy Performance of an Asynchronous MIPS R3000 Microprocessor

Abstract

This paper presents the speed and energy figures for an asynchronous implementation of a MIPS R3000 microprocessor. The design is almost entirely QDI and introduces a new fine-grained pipeline. The performance figures show that this design is four times as efficient as equivalent clocked designs and that its cycle time in FO4 units compares to that of high-performance dynamic pipelines.

Additional Information

© 2001 California Institute of Technology. The research described in this paper was sponsored by the Defense Advanced Research Projects Agency and monitored by the Air Force under contract F29601-00-K-0184.

Attached Files

Submitted - 2001_mipsresults.ps

Submitted - CSTR2001.pdf

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