Pipelined Asynchronous Circuits
- Creators
- Lines, Andrew Matthew
Abstract
This thesis presents a design style for implementing communicating sequential processes (CSP) as quasi delay insensitive asynchronous circuits, based on the compilation method of [1]. Although hand compilation can always yield optimal circuits to a good designer, a restricted approach is suggested which can easily implement circuits with some slack between inputs and outputs. These circuits are fast and versatile building blocks for highly pipelined designs. The first chapter presents the implementation approach for individual cells. The second chapter investigates the time behavior of complex pipelined circuits, with the goal of adding slack where necessary and adjusting transistor sizes to optimize the overall throughput.
Additional Information
© 1998 California Institute of Technology. June 1995, revised June 1998.Attached Files
Submitted - CSTR1998.pdf
Submitted - postscript.ps
Files
Name | Size | Download all |
---|---|---|
md5:79861ab4a8cb0f9aa710e2cd93b1ec5b
|
349.0 kB | Preview Download |
md5:4fe88e313482776ddd12f4db142aded3
|
862.2 kB | Download |
Additional details
- Eprint ID
- 26834
- Resolver ID
- CaltechCSTR:1998.cs-tr-95-21
- Created
-
2001-04-30Created from EPrint's datestamp field
- Updated
-
2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports