Published January 1, 1993
| Submitted
Technical Report
Open
An Asynchronous Microprocessor in Gallium Arsenide
Chicago
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Abstract
In this paper, several techniques for designing asynchronous circuits in Gallium Arsenide are presented. Several new circuits were designed, to implement specific functions necessary to the design of a full microprocessor. A sense-amplifier, a completion tree, and a general circuit structure for operators specified by production rules are introduced. These circuit were used and tested in a variety of designs, including two asynchronous microprocessors and two asynchronous static RAM's. One of the microprocessor runs at over 100 MIPS with a power consumption of 2 Watts.
Additional Information
© California Institute of Technology. We are indebted to Marcel van der Goot for his help in generating high quality software support. Acknowledgment is due to Steve Burns and Pieter Hazewindus, for their participation in the original design, and many very useful comments and conversations, and H. Peter Hofstee for his collaboration in the design of asynchronous memories. Many thanks to Ray Milano of Vitesse Semiconductors, for invaluable help with the HGAAS technology, and to Cindy Hibbert and Metasoftware, for their help with Hspice. The research described in this paper was sponsored by the Defense Advanced Research Projects Agency, DARPA Order number 6202, and monitored by the Office of Naval Research under contract number N00014-87-K-0745.Attached Files
Submitted - CS_TR_93_38.pdf
Submitted - postscript.ps
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Additional details
- Eprint ID
- 26779
- Resolver ID
- CaltechCSTR:1993.cs-tr-93-38
- Defense Advanced Research Projects Agency (DARPA)
- 6202
- Office of Naval Research (ONR)
- N00014-87-K-0745
- Created
-
2001-04-25Created from EPrint's datestamp field
- Updated
-
2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports