Performance Analysis and Optimization of Asynchronous Circuits Produced by Martin Synthesis

Abstract

We present a method for analyzing the timing performance of asynchronous circuits, in particular, those derived by program transformation from concurrent programs using the synthesis approach developed by Martin. The analysis method produces a performance metric (related to the time needed to perform an operation) in terms of the primitive gate delays of the circuit. Because the gate delays are functions of transistor sizes, the performance metric can be optimized with respect to these sizes. For a large class of asynchronous circuits -- including those produced by the Martin synthesis -- these techniques produce the global optimum of the performance metric. A CAD tool has been implemented to perform this optimization.

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