HEX: A Hierarchical Circuit Extractor

Abstract

This report describes the algorithm, implementation, and performance of a hierarchical circuit extractor, HEX, for Metal-Oxide Semiconductor(M0S) layout designs at Caltech. The input to HEX is a layout design in Caltech intermediate Form(CIF), a hierarchical layout description language, and the output is a hierarchical netlist describing the circuit. HEX avoids redundant work by finding out the repetitive cells in the input CIF file. To handle overlapping instances, HEX modifies the hierarchy in the CIF file to generate a new one without overlapping instances. HEX then traverses the resulting hierarchical structure, calls a flat extractor to extract leaf cells and composes cells bottom up to get the circuit information of the whole chip.

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