Switch-Level Model and Simulator for MOS Digital Systems
- Creators
- Bryant, Randal E.
Abstract
The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state "open", "closed", or "indeterminate". Many characteristics of 140S circuits can be modeled accurately, including: ratioed, complementary, and precharged logic-, dynamic and static storage; (bidirectional) pass transistors; busses; charge sharing; and sneak pa ths. In this paper we present a formal development of the switch-level model starting from a description of circuit behavior in terms of switch graphs. Then we describe an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra. This algorithm has been implemented in the simulator MOSSIM II and has been used to simulate circuits containing over 10,000 transistors. By developing a formal theory of MOS logic circuits, we have achieved a greater degree of generality and accuracy than is found in other logic simulators for MOS.
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Additional details
- Eprint ID
- 26665
- Resolver ID
- CaltechCSTR:1983.5065-tr-83
- Created
-
2001-04-24Created from EPrint's datestamp field
- Updated
-
2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports