Welcome to the new version of CaltechAUTHORS. Login is currently restricted to library staff. If you notice any issues, please email coda@library.caltech.edu
Published January 1, 1983 | public
Report Open

Switch-Level Model and Simulator for MOS Digital Systems

Abstract

The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state "open", "closed", or "indeterminate". Many characteristics of 140S circuits can be modeled accurately, including: ratioed, complementary, and precharged logic-, dynamic and static storage; (bidirectional) pass transistors; busses; charge sharing; and sneak pa ths. In this paper we present a formal development of the switch-level model starting from a description of circuit behavior in terms of switch graphs. Then we describe an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra. This algorithm has been implemented in the simulator MOSSIM II and has been used to simulate circuits containing over 10,000 transistors. By developing a formal theory of MOS logic circuits, we have achieved a greater degree of generality and accuracy than is found in other logic simulators for MOS.

Files

postscript.pdf
Files (4.1 MB)
Name Size Download all
md5:5eeb4ab6baab3ea43924a4b17438ea1b
1.8 MB Preview Download
md5:8d068187b26d2ab3714b456bae9d4826
2.3 MB Download

Additional details

Created:
August 19, 2023
Modified:
December 22, 2023