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Published July 18, 2008 | Submitted
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Hierarchical power routing

Abstract

Advances in LSI technology allow the system designer to implement large amounts of processing capability on a single silicon chip. It will soon be possible to construct a large number of processing elements on these chips. How will the system designer organize these processing elements? Hierarchically designed array or tree machines arc two possible alternatives. This paper provides a background for study of array and tree machines by examining how to supply power to an array of processing elements.

Additional Information

Series numbering on title page: MEMO 2069

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Submitted - 2069-TR-78.pdf

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Created:
August 19, 2023
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January 13, 2024