Published October 17, 1978
| Submitted
Technical Report
Open
Hierarchical power routing
- Creators
- Johannsen, Dave
Chicago
An error occurred while generating the citation.
Abstract
Advances in LSI technology allow the system designer to implement large amounts of processing capability on a single silicon chip. It will soon be possible to construct a large number of processing elements on these chips. How will the system designer organize these processing elements? Hierarchically designed array or tree machines arc two possible alternatives. This paper provides a background for study of array and tree machines by examining how to supply power to an array of processing elements.
Additional Information
Series numbering on title page: MEMO 2069Attached Files
Submitted - 2069-TR-78.pdf
Files
2069-TR-78.pdf
Files
(3.1 MB)
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Additional details
- Eprint ID
- 27099
- DOI
- 10.7907/Z94F1NP4
- Resolver ID
- CaltechCSTR:1978.2069-tr-78
- Created
-
2008-07-18Created from EPrint's datestamp field
- Updated
-
2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports
- Series Name
- Computer Science Technical Memorandum
- Series Volume or Issue Number
- 1978.2069