Published February 2007
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A 90nm CMOS 16Gb/s transceiver for optical interconnects
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Abstract
An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and an integrating/double-sampling RX to eliminate the need for a bit-rate TIA. A dual-loop CDR with baud-rate phase detection further reduces power and area. Fabricated in a 1V 90nm CMOS process, the transceiver achieves 16Gb/s operation while consuming 129mW and occupying 0.105mm^2.
Additional Information
© 2000 IEEE. Reprinted with permission. Publication Date: 11-15 Feb. 2007. The authors would like to acknowledge the help and support of D. Patil, B. Nezamfar, P. Chiang, and B. Gupta, CMP and STMicroelectronics for chip fabrication, ULM photonics for VCSELs, Albis Optoelectronics for photodiodes, and MARCO-IFC for funding.Attached Files
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Additional details
- Eprint ID
- 10797
- Resolver ID
- CaltechAUTHORS:PALisscc07
- Microelectronics Advanced Research Corporation (MARCO)
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2008-06-11Created from EPrint's datestamp field
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2023-03-15Created from EPrint's last_modified field