Published June 2004
| Published
Book Section - Chapter
Open
CMOS transceiver with baud rate clock recovery for optical interconnects
Chicago
An error occurred while generating the citation.
Abstract
An efficient baud rate clock and data recovery architecture is applied to a double sampling/integrating front-end receiver for optical interconnects. Receiver performance is analyzed and projected for future technologies. This front-end allows use of a 1:5 demux architecture to achieve 5Gb/s in a 0.25 μm CMOS process. A 5:1 multiplexing transmitter is used to drive VCSELs for optical transmission. The transceiver chip consumes 145mW per link at 5Gb/s with a 2.5V supply.
Additional Information
© 2004 IEEE. Reprinted with Permission. Publication Date: 17-19 June 2004. Posted online: 2004-10-25. The authors would like to thank Jaeha Kim, Elad Alon, Aparna Bhatnagar and Tim Drabik for technical discussions, National Semiconductor for fabrication of the test chip, and NSF, TI, DARPA, and the MARCO Interconnect Focus Center for funding.Attached Files
Published - EMAvlsic04.pdf
Files
EMAvlsic04.pdf
Files
(321.5 kB)
| Name | Size | Download all |
|---|---|---|
|
md5:f6a5761af2963ece82f1001e18ea94e3
|
321.5 kB | Preview Download |
Additional details
- Eprint ID
- 10570
- Resolver ID
- CaltechAUTHORS:EMAvlsic04
- NSF
- Texas Instruments
- Defense Advanced Research Projects Agency (DARPA)
- Microelectronics Advanced Research Corporation (MARCO)
- Created
-
2008-05-19Created from EPrint's datestamp field
- Updated
-
2023-03-15Created from EPrint's last_modified field