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Published April 2007 | Published
Journal Article Open

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

Abstract

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10^-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally.

Additional Information

© 2007 IEEE. Reprinted with permission. Manuscript received August 25, 2006; revised December 19, 2006. [Posted online: 2007-03-26] This work was supported in part by MPO Contract H98230-04-C-0920.

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Created:
August 22, 2023
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October 16, 2023