Array-based architecture for FET-based, nanoscale electronics
- Creators
- DeHon, André
Abstract
Advances in our basic scientific understanding at the molecular and atomic level place us on the verge of engineering designer structures with key features at the single nanometer scale. This offers us the opportunity to design computing systems at what may be the ultimate limits on device size. At this scale, we are faced with new challenges and a new cost structure which motivates different computing architectures than we found efficient and appropriate in conventional very large scale integration (VLSI). We sketch a basic architecture for nanoscale electronics based on carbon nanotubes, silicon nanowires, and nano-scale FETs. This architecture can provide universal logic functionality with all logic and signal restoration operating at the nanoscale. The key properties of this architecture are its minimalism, defect tolerance, and compatibility with emerging bottom-up nanoscale fabrication techniques. The architecture further supports micro-to-nanoscale interfacing for communication with conventional integrated circuits and bootstrap loading.
Additional Information
"©2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." Received July 27, 2002; revised October 22, 2002. This work was supported by the Defense Advanced Research Project Agency (DARPA) Moletronics Program under Grant ONR N00014-01-0651.Files
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Additional details
- Eprint ID
- 1030
- Resolver ID
- CaltechAUTHORS:DEHieeetn03a
- Created
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2005-12-02Created from EPrint's datestamp field
- Updated
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2021-11-08Created from EPrint's last_modified field