Programmable neural logic
- Creators
- Bohossian, Vasken
- Hasler, Paul
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Bruck, Jehoshua
Abstract
Circuits of threshold elements (Boolean input, Boolean output neurons) have been shown to be surprisingly powerful. Useful functions such as XOR, ADD and MULTIPLY can be implemented by such circuits more efficiently than by traditional AND/OR circuits. In view of that, we have designed and built a programmable threshold element. The weights are stored on polysilicon floating gates, providing long-term retention without refresh. The weight value is increased using tunneling and decreased via hot electron injection. A weight is stored on a single transistor allowing the development of dense arrays of threshold elements. A 16-input programmable neuron was fabricated in the standard 2 μm double-poly, analog process available from MOSIS. We also designed and fabricated the multiple threshold element introduced in [5]. It presents the advantage of reducing the area of the layout from O(n^2) to O(n); (n being the number of variables) for a broad class of Boolean functions, in particular symmetric Boolean functions such as PARITY. A long term goal of this research is to incorporate programmable single/multiple threshold elements, as building blocks in field programmable gate arrays.
Additional Information
© Copyright 1998 IEEE. Reprinted with permission. Manuscript received March 22, 1998; revised August 7, 1998. This work was presented in part at the Second IEEE International Conference on Innovative Systems in Silicon, Austin, TX, October 1997. This work was supported in part by the NSF Young Investigator Award CCR-9457811, by the Sloan Research Fellowship, by a grant from the IBM Almaden Research Center, San Jose, CA, by the Center for Neuromorphic Systems Engineering as a part of the National Science Foundation Engineering Research Center Program; and by the California Trade and Commerce Agency, Office of Strategic Technology. The authors would like to thank the reviewers for their comments and V. Koosh for helping with the testing and analysis of the chip.Attached Files
Published - BOHieeetcpmtb98.pdf
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Additional details
- Eprint ID
- 11518
- Resolver ID
- CaltechAUTHORS:BOHieeetcpmtb98
- National Science Foundation
- CCR-9457811
- Alfred P. Sloan Foundation
- IBM Almaden Research Center
- Center for Neuromorphic Systems Engineering, Caltech
- California Trade and Commerce Agency, Office of Strategic Technology
- Created
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2008-08-28Created from EPrint's datestamp field
- Updated
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2021-11-08Created from EPrint's last_modified field