Published February 1987
| Published
Journal Article
Open
On the Time-Bandwidth Proof in VLSI Complexity
- Creators
- Abu-Mostafa, Yaser S.
Chicago
An error occurred while generating the citation.
Abstract
A subtle fallacy in the original proof [1] that the computation time T is lowerbounded by a factor inversely proportional to the minimum bisection width of a VLSI chip is pointed out. A corrected version of the proof using the idea of conditionally self-delimiting messages is given.
Additional Information
© 1987 IEEE. Reprinted with permission. Manuscript received July 18, 1985; revised October 15, 1985. This work was supported by the Program in Advanced Technologies (Aerojet, GM, GTE, TRW).Attached Files
Published - ABUieeetc87.pdf
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ABUieeetc87.pdf
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Additional details
- Eprint ID
- 7011
- Resolver ID
- CaltechAUTHORS:ABUieeetc87
- Caltech Program in Advanced Technologies
- Created
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2007-01-05Created from EPrint's datestamp field
- Updated
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2021-11-08Created from EPrint's last_modified field