FMC Daughter Board Stacking on SNAP2: Signal Integrity Tests For LWA352 Digitizers

Abstract

The digital processing design for LWA352 includes use of SNAP2 FPGA boards [1] for the initial processing stage, including the F engine and cosmic ray detection. Calculations and benchmarking show [2] that the Xilinx Ultrascale XCKU115FLVF1924 FPGA on the SNAP2 board has sufficient processing and I/O capacity to handle at least 64 separate signals. However, creating enough digitizer channels to accept 64 analog signals and to deliver their quantized samples to the SNAP2 is challenging. ADC chips capable of nearly 200 MHz sampling rate can handle at most 4 signals each, so 16 such chips are needed. On the analog side, connectors for delivering those signals to the ADCs necessarily occupy significant PCB area, especially since they must be kept well separated to avoid cross-talk. For available ADC chips, the digitized output is provided via multiple high-speed LVDS streams. For such signals, the most suitable digital interface from digitizer boards to the SNAP2 is the FPGA Mezzanine Card (FMC) connector. The SNAP2 has two high-pin-count FMC connectors, each with 400 pins. We have verified that each of these has sufficient LVDS pairs routed to the FPGA to support 32 signals. The FMC concept is that a daughter board ("mezzanine card") plugs into the mother board ("carrier card"). Figure 1 includes a photograph of a SNAP2 board showing its two FMC connectors with no mezzanine cards, and with a card plugged into the "left" connector. That mezzanine card (from the Chinese Institute of Automation, IoA) has size 69.0 x 84.2 mm and fits within the space allowed for it on the SNAP2. There are standard form factors for FMC-compliant mezzanine cards, but we are designing our own digitizer boards and we are not constrained to use those form factors. Nevertheless, the SNAP2 layout limits the width of FMC cards to 76 mm if both connectors are used. The length can be considerably larger than that of the card shown in Fig 1 if we are willing to have it cantilevered beyond the edge of the SNAP2. We will do that for our boards. With these constraints, we find that we are unable to handle more than 16 signals on a single digitizer board, even when it is constructed as a 10-layer board. A preliminary rendering of such a board is shown in Figure 2. It uses 16 MMCX coax connectors for its analog inputs, and 4 Texas Instruments ADS5296A quad-ADC chips. To deliver 32 digitized signals to one FMC connector, we plan to stack two such boards, with the upper and lower boards using different FMC pins for their output LVDS streams and clocks but common pins for power and control. The lower board requires an FMC carrier-card connector on its upper side and an FMC mezzanine-card connector on its lower side, with selected pins connected directly from one side to the other. A concern with this arrangement is whether the integrity of the high-speed LVDS signals can be maintained across two mated FMC connector pairs and through the lower board. This report describes tests that demonstrate satisfactory performance in that situation.

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