A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS

Abstract

This paper describes a 4-level pulse-amplitude modulation (PAM4) wireline receiver incorporating a continuous time linear equalizer (CTLE) and a 2-tap direct decision feedback equalizer (DFE). A track-and-regenerate CMOS slicer is proposed and employed in the PAM4 receiver. The reduced delay of the proposed slicer and its full-swing outputs allow the implementation of 2-tap direct decision-feedback equalization at 60-Gb/s with improved energy efficiency and area requirements. Fabricated in 28-nm CMOS technology, the PAM4 receiver achieved BER better than 1E-12 at 60-Gb/s with 1.1 pJ/b energy efficiency measured over a channel of 8.2dB loss at Nyquist rate.

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