A static RAM chip with on-chip error correction

Abstract

This paper describes a 2-kb CMOS static RAM with on-chip error-correction capability (ECCRAM chip). The chip employs the linear sum code (LSC) technique to perform error detection and correction. The ECCRAM chip has been fabricated in a double-metal scalable CMOS process with 3-µm feature size. Testing results of the actual chip shows a significant improvement in random error tolerance.

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