Published August 16, 1979
| Published
Journal Article
Open
Electrical properties of silicon-implanted furnace-annealed silicon-on-sapphire devices
- Creators
- Roulet, M. E.
- Schwob, P.
- Golecki, I.
- Nicolet, M.-A.
Chicago
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Abstract
The crystalline quality of s.o.s. layers can be improved near the silicon-sapphire interface by silicon implantation followed by recrystallisation. Device performance on such layers is markedly improved as to n-channel m.o.s.t. noise and leakage current, reverse diode current and lateral bipolar transistor gain. Minority-carrier lifetimes up to 50 ns are deduced.
Additional Information
© 1979 The Institution of Electrical Engineers. 2nd July 1979. The authors would like to thank S. S. Lau for the r.e.d. measurements and D. Tonn for technical assistance (Caltech). Stimulating discussions with J. Fellrath of CEH are gratefully acknowledged. This work has been supported by the Office of Naval Research (L. Cooper) and by the Swiss Foundation for the Encouragement of Applied Research.Attached Files
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Additional details
- Eprint ID
- 79875
- Resolver ID
- CaltechAUTHORS:20170807-155031287
- Office of Naval Research (ONR)
- Swiss Foundation for the Encouragement of Applied Research
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2017-08-07Created from EPrint's datestamp field
- Updated
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2021-11-15Created from EPrint's last_modified field