Published June 1980
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Design Integrity and Immunity Checking: A New Look at Layout Verification and Design Rule Checking
- Creators
- McGrath, Edward J.
- Whitney, Telle
Abstract
A program implementing a novel approach to layout verification is presented. The approach uses topological and device information to eliminate most false and unchecked errors. This technique, coupled with a hierarchical front end to eliminated redundant checks, is appropriate for layout verification of VLSI designs. Design rules appropriate for this technique, some usage rules in the context of structured design, and a discussion of the future of design rule checking are also presented.
Additional Information
© 1980 IEEE. We would like to express our gratitude to the participants in the Silicon Structures Project at Caltech for all the support and encouragement they gave during this work. Special thanks go out to Ivan Suthcrland, Don Oestreicher, Jim Kajiya, Ricky Mosteller and Eric Barton for specific suggestions and help during the course of this work. Credit is due to Don Oestreicher for the exposure function calculations.Attached Files
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Additional details
- Eprint ID
- 79788
- Resolver ID
- CaltechAUTHORS:20170802-153857139
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