Optoelectronic Chip for the Implementation of Back Error Propagation

Abstract

We present a CMOS silicon chip that optically implements the back error propagation (BEP) algorithm [1] of a two layer neural network. The chip has eight units (or "neurons") on a area of approximately 2x2 mm. Each unit consists of a phototransistor as the detector, a modulator pad for light modulation, sample-and-hold circuits, and additional circuits necessary to perform the BEP algorithm.

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