Published December 2009
| Published
Book Section - Chapter
Open
Asynchronous logic for high variability nano-CMOS
- Creators
- Martin, Alain J.
Chicago
Abstract
At the nanoscale level, parameter variations in fabricated devices cause extreme variability in delay. Delay variations are also the main issue in subthreshold operation. Consequently, asynchronous logic seems an ideal, and probably unavoidable choice, for the design of digital circuits in nano CMOS or other emerging technologies. This paper examines the robustness of one particular asynchronous logic: quasi-delay insensitive or QDI. We identify the three components of this logic that can be affected by extreme variability: staticizer, isochronic fork, and rings. We show that staticizers can be eliminated, and isochronic forks and rings can be made arbitrarily robust to timing variations.
Additional Information
© 2009 IEEE. The research described in this paper was supported by a grant from the National Science Foundation.Attached Files
Published - 05410925.pdf
Files
05410925.pdf
Files
(210.5 kB)
Name | Size | Download all |
---|---|---|
md5:aee85d1a360ad1f8aee22eb732e435b2
|
210.5 kB | Preview Download |
Additional details
- Eprint ID
- 75263
- Resolver ID
- CaltechAUTHORS:20170320-175344479
- NSF
- Created
-
2017-03-21Created from EPrint's datestamp field
- Updated
-
2021-11-15Created from EPrint's last_modified field