Published February 2013
| public
Book Section - Chapter
Reconfigurable processor for energy-scalable computational photography
Abstract
Computational photography applications, such as lightfield photography [1], enable capture and synthesis of images that could not be captured with a traditional camera. Non-linear filtering techniques like bilateral filtering [2] form a significant part of computational photography. These techniques have a wide range of applications, including High-Dynamic Range (HDR) imaging [3], Low-Light Enhanced (LLE) imaging [4], tone management and video enhancement. The high computational complexity of such multimedia processing applications necessitates fast hardware implementations [5] to enable real-time processing. This paper describes a hardware implementation of a reconfigurable multi-application processor for computational photography.
Additional Information
© 2013 IEEE. This work was funded by Foxconn Technology Group. The authors thank TSMC University Shuttle Program for chip fabrication and Prof. Fredo Durand and Jonathan Regan-Kelley for valuable feedback and suggestions.Additional details
- Eprint ID
- 73837
- Resolver ID
- CaltechAUTHORS:20170130-171410598
- Foxconn Technology Group
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2017-01-31Created from EPrint's datestamp field
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2021-11-11Created from EPrint's last_modified field