Published March 2010
| public
Book Section - Chapter
A Resilience Roadmap
- Creators
- Nassif, Sani R.
- Mehta, Nikil
- Cao, Yu
Abstract
Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults. This paper examines the issue of circuit resilience, then proposes and demonstrates a roadmap for evaluating fault rates starting at the 45nm and going down to the 12nm nodes. The complete infrastructure necessary to make these predictions is placed in the open source domain, with the hope that it will invigorate research in this area.
Additional Information
© 2010 EDAA. The authors want to gratefully acknowledge the contributions of Juan-Antonio Carballo, Chris Wilkerson, and Larry Wissel to the development of this roadmap; and thank Andre DeHon, Heather Quinn and Helmut Graeb for comments on this paper. This material is based upon work supported by the National Science Foundation under Grant No. 0637190 to the Computing Research Association. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Computing Research Association or the National Science Foundation.Additional details
- Eprint ID
- 72610
- Resolver ID
- CaltechAUTHORS:20161206-160547566
- 0637190
- NSF
- Created
-
2016-12-07Created from EPrint's datestamp field
- Updated
-
2019-10-03Created from EPrint's last_modified field