A 25 Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication
Abstract
Integrating optical receivers based on double-sampling architecture exhibit a low-power alternative to those designed around transimpedance amplifiers (TIA). In this paper, we present a 3D-integrated CMOS/silicon-photonic optical receiver. The receiver features a low-bandwidth TIA integrating front-end double-sampling technique and dynamic offset modulation. The copper-pillar-based 3D-integration technology used here enables ultralow parasitics and 40 μm pitch for interconnection. We study different tradeoffs in designing an optical receiver and how to choose between a full-bandwidth TIA front-end and integrating architecture using a resistive front-end or a low-bandwidth TIA front-end. The design methodology is supported by measurements of two 3D-integrated prototypes based on a conventional TIA and a double-sampling integrating receiver. The proposed receiver architecture achieves −14.9 dBm of sensitivity and energy efficiency of 170 fJ/b at 25 Gb/s, while the conventional receiver achieves a sensitivity of −10.4 dBm and energy efficiency of 260 fJ/b at 21.2 Gb/s.
Additional Information
© 2015 IEEE. Manuscript received July 22, 2015; revised September 25, 2015; accepted October 15, 2015. Date of publication October 25, 2015; date of current version June 1, 2016. The authors would like to thank ST Microelectronics for chip fabrication.Additional details
- Eprint ID
- 68595
- DOI
- 10.1109/JLT.2015.2494060
- Resolver ID
- CaltechAUTHORS:20160622-132148230
- Created
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2016-06-23Created from EPrint's datestamp field
- Updated
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2023-03-15Created from EPrint's last_modified field