Published September 2015
| public
Book Section - Chapter
Designing a SoC to Control the Next-Generation Space Exploration Flight Science Instruments
Chicago
Abstract
SoC technology permits to integrate all the computational power required by next-generation space exploration flight science instruments on a single chip. This paper describes the Xilinx Zynq-based Advanced Processor for space EXploration SoC (APEX-SoC) that has been developed at the Jet Propulsion Laboratory (JPL) in collaboration with ARM. The paper discusses the APEX-SoC architecture and demonstrates its main capabilities when used to control JPL's Compositional InfraRed Imaging Spectrometer (CIRIS). As the CIRIS instrument is intended to explore harsh space environments, the paper also deals with the Radiation Hardened By Design (RHBD) features that have been implemented in the APEX-SoC.
Additional Information
© 2015 by IEEE. The research described in this paper was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration (NASA). Xabier Iturbe is funded by the European Commision's FP7 Marie-Curie International Outgoing Fellowship Program with "Project No. 627579".Additional details
- Eprint ID
- 64534
- Resolver ID
- CaltechAUTHORS:20160217-102735409
- NASA/JPL/Caltech
- Marie Curie Fellowship
- 627579
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2016-02-17Created from EPrint's datestamp field
- Updated
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2021-11-10Created from EPrint's last_modified field