A 25Gbps 3D-Integrated CMOS/Silicon Photonic Optical Receiver with -15dBm Sensitivity and 0.17pJ/bit Energy Efficiency

Abstract

With continuous demand for higher bandwidth chip-to-chip communication, signaling over wires has become extremely challenging [1]. Optical signaling is an attractive alternative due to its small frequency-dependent loss and higher bandwidth. Recent advances in silicon photonic devices and 3D integration [2] have enabled them to be a viable solution for dense chip-to-chip interconnection. A key design metric for interconnects is the link power efficiency at a specific distance. In a modulator-based optical link, power is dissipated not only in the electronic circuitry, but also in the laser source. Improving the sensitivity of the receiver, which translates to lower laser power, can significantly reduce the power consumption of the link. In this work, a highly sensitive receiver topology is presented that is suitable for ultra-low capacitance frontends.

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