Pooh: A Uniform Representation For Circuit Level Designs

Abstract

This paper describes a simple but general, technology independent representation for VLSI circuits which maintains connectivity, circuit schematic, and mask geometry information. A transistor level cell is represented as the interconnection of devices along with their types, sizes and placement, and the cell's typed ports. Connection is represented explicitly by shared connection points. A file of technology dependent information indicates how to implement each transistor type, interconnect type and connection point type, as well as how structure types may interact.

Additional details