Published April 1976
| Published
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A two's complement pipeline multiplier
- Creators
- Cheng, Edmund K.
-
Mead, Carver A.
Chicago
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Abstract
A serial-data pipeline multiplier was designed and implemented in p-channel silicon-gate MOS. It uses a radix-4 Booth algorithm for two's complement compatibility. The circuit is modular, and is configured to multiply one data word by two coefficient words simultaneously.
Additional Information
© 1976 IEEE. The authors wish to thank R. F. Jurgens, R. T. Maaumoto, and G. A. Morris for their assistance; Intel Corp. for fabrication of the circuits; and in particular R. F. Lyon for his invaluable contributions during the butial phase of this work.Attached Files
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Additional details
- Eprint ID
- 53905
- Resolver ID
- CaltechAUTHORS:20150120-163927542
- Intel Corporation
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2015-01-21Created from EPrint's datestamp field
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2021-11-10Created from EPrint's last_modified field