The matching of small capacitors for analog VLSI
Abstract
The capacitor has become the dominant passive component for analog circuits designed in standard CMOS processes. Thus, capacitor matching is a primary factor in determining the precision of many analog circuit techniques. In this paper, we present experimental measurements of the mismatch between square capacitors ranging in size from 6 μm×6 μm to 20 μm×20 μm fabricated in a standard 2 μm double-poly CMOS process available through MOSIS. For a size of 6 μm×6 μm, we have found that those capacitors that fell within one standard deviation of the mean matched to better than 1%. For the 20 μm×20 μm size, we observed that those capacitors that fell within 1 standard deviation of the mean matched to about 0.2%. Finally, we observed the effect of nonidentical surrounds on capacitor matching.
Additional Information
© 1996 IEEE. This work is supported in part by the Office of Naval Research, by the Advanced Research Projects Agency, by the Beckman Foundation, and by the Center for Neuromorphic Systems Engineering as a part of the National Science Foundation Engineering Research Center Program, and by the California Trade and Commerce Agency, Office of Strategic Technology.Attached Files
Published - 00539873.pdf
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Additional details
- Eprint ID
- 53649
- Resolver ID
- CaltechAUTHORS:20150113-154605832
- Office of Naval Research (ONR)
- Advanced Research Projects Agency (ARPA)
- NSF
- California Trade and Commerce Agency, Office of Strategic Technology
- Created
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2015-01-14Created from EPrint's datestamp field
- Updated
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2021-11-10Created from EPrint's last_modified field