Wireline Transceivers

Abstract

High-bandwidth wireline communication continues to be crucial for many electronic systems today. Numerous research efforts are dedicated to enhance speed, power efficiency, flexibility, and ease-of-use of these transceivers. This session includes some of the latest advances in this domain. The first transceiver paper employs a sub-sampling ring oscillator phase-locked loop (PLL) to obtain a large frequency range with low jitter performance. The PLL is one of the most important blocks in a high-speed I/O link that generates the clocks for the receiver and transmitter of the system. In this paper the transmitter achieves 160fs RMS jitter and 10.9ps total jitter at 15.625 Gbps.

Additional details