Quantifying Near-Threshold CMOS Circuit Robustness
Abstract
In order to build energy efficient digital CMOS circuits, the supply voltage must be reduced to near-threshold. Problematically, due to random parameter variation, supply scaling reduces circuit robustness to noise. Moreover, the effects of parameter variation worsen as device dimensions diminish, further reducing robustness, and making parameter variation one of the most significant hurdles to continued CMOS scaling. This paper presents a new metric to quantify circuit robustness with respect to variation and noise along with an efficient method of calculation. The method relies on the statistical analysis of standard cells and memories resulting an an extremely compact representation of robustness data. With this metric and method of calculation, circuit robustness can be included alongside energy, delay, and area during circuit design and optimization.
Additional Information
© 2014 California Institute of Technology.Attached Files
Submitted - snm.pdf
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Additional details
- Eprint ID
- 52152
- Resolver ID
- CaltechAUTHORS:20141125-133400175
- Created
-
2014-11-25Created from EPrint's datestamp field
- Updated
-
2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports
- Series Name
- Computer Science Technical Reports
- Series Volume or Issue Number
- 2014.002