Published June 2012
| public
Book Section - Chapter
A low-power 20Gb/s transmitter in 65nm CMOS technology
Chicago
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Abstract
A 20Gb/s transmitter employing an analog filtering pre-emphasis equalization technique is presented. The transmitter dissipates 10mW from a 1.2V supply and occupies 0.01mm2. This high-frequency boosting equalization technique allows for compensating channel losses up to 20dB at Nyquist-rate. The prototype was fabricated in 65nm CMOS technology and characterized using lossy cables and 5" and 10" FR4 PCB traces.
Additional Information
©2012 IEEE. The authors acknowledge the support of NSF and Intel as well as STMicroelectronics for fabricating the chip. M. Nazari would like to thank Z. Safarian for constant help and support.Additional details
- Eprint ID
- 48748
- Resolver ID
- CaltechAUTHORS:20140820-153017399
- NSF
- Intel
- STMicrolectronics
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2014-08-20Created from EPrint's datestamp field
- Updated
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2023-03-15Created from EPrint's last_modified field