Published April 23, 2012
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Chip assembly tools
- Creators
- Trimberger, Stephen
- Kingsley, Chris
Abstract
In large-scale integrated circuit design, chip assembly is more difficult, more time consuming. and more error prone than the design of the low-level cells. Assembly errors tend to persist until late in the design cycle requiring extensive rework. Unfortunately, the tools traditionally provided for custom integrated circuit design address the problems of cell design well, but do not properly address the problems of chip assembly. A great deal of emphasis at Caltech has been placed on tools that do address chip assembly. This paper reports on some of these tools.
Additional Information
We would like to thank those people at Caltech who have allowed us to report on their work, notably Dave Johannsen, for Bristle Blocks; and John Tanner, the author of Comped. The work reported in this paper was supported by the Caltech Silicon Structures Project and by the United States Department of Defense Advanced Research Projects Agency.Files
TM_5005.pdf
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Additional details
- Eprint ID
- 30254
- Resolver ID
- CaltechAUTHORS:20120423-105037951
- Caltech Silicon Structures Project
- Defense Advanced Research Projects Agency (DARPA)
- Created
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2012-04-23Created from EPrint's datestamp field
- Updated
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2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports
- Other Numbering System Name
- Computer Science Technical Memorandum
- Other Numbering System Identifier
- 5005