Concurrent fault simulation of MOS digital circuits
- Creators
- Schuster, Michael D.
- Bryant, Randal E.
Abstract
The concurrent fault simulation technique is widely used to analyse the behavior of digital circuits in the presence of faults. We show how this technique can be applied to metal-oxide-semiconductor (MOS) digital circuits when modeled at the switch-level as a set of charge storage nodes connected by bidirectional transistor switches. The algorithm we present is capable of analysing the behavior of a wide variety of MOS circuit failures, such as stuck-at-zero or stuck-at-one nodes, stuck-open or stuck-closed transistors, or resistive opens or shorts. We have implemented a fault simulator FMOSSIM based on this algorithm. The capabilities and the peformance of this program demonstrate the advantages of combining switch-level and concurrent simulation techniques.
Additional Information
© Artech House, 1984. To be presented at the Conference on Advanced Research in VLSI, to be held at the Massachusetts Institute of Technology, January 1984. Proceedings published by Artech House, Inc:., Dedham, MA 02026. This research was supported in part by the IBM Corporation and by the Defense Advanced Research Contracts Agency, ARPA Order 3771. Michael Schuster was supported in part by a Bell Laboratories Ph.D. Scholarship.Files
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Additional details
- Eprint ID
- 30231
- Resolver ID
- CaltechAUTHORS:20120420-114600956
- IBM Corporation
- ARPA order 3771
- Defense Advanced Research Projects Agency (DARPA)
- Bell Laboratories
- Created
-
2012-05-02Created from EPrint's datestamp field
- Updated
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2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports
- Other Numbering System Name
- Computer Science Technical Memorandum
- Other Numbering System Identifier
- 5101