Published August 4, 1983
| public
Technical Report
Open
Minimum propagation delays in VLSI
- Creators
-
Mead, Carver
- Rem, Martin
Chicago
Abstract
In this paper we demonstrate that it is possible to achieve propagation delays that are logarithmic in the lengths of the wires, provided the connection pattern is designed to meet rather strong constraints. These constraints are, in effect, satisfied only by connection patterns that exhibit a hierarchical structure. We also show that, even at the ultimate physical limits of the technology, the propagation for reasonably sized VLSI chips is dominated by these considerations, rather than by the speed of light.
Additional Information
Copyright, California Institute of Technology, 1981. The research described in this paper was sponsored by the Office of Naval Research Contract No. N00014-76-C-0367 and by the Defense Advanced Research Agency, ARPA Order number 3771, and monitored by the Office of Naval Research under Contract number N00014-79-C-0597.Files
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Additional details
- Eprint ID
- 30220
- Resolver ID
- CaltechAUTHORS:20120420-104637505
- Office of Naval Research
- N00014-76-C-0367
- Defense Advanced Research Projects Agency (DARPA)
- ARPA order 3771
- Created
-
2012-05-02Created from EPrint's datestamp field
- Updated
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2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports
- Other Numbering System Name
- Computer Science Technical Memorandum
- Other Numbering System Identifier
- 4601