Published May 1992
| Published
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VLSI decompositions for deBruijn graphs
- Creators
- Dolinar, Sam
- Ko, Tsz-Mei
- McEliece, Robert J.
Chicago
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Abstract
A C-chip VLSI decomposition of a graph G is a collection of C isomorphic disjoint subgraphs of G (the building blocks), which together contain all of G's vertices. The efficiency of such a decomposition is defined to be the fraction of edges of G that are in the building block. Motivated by the need to construct large Viterbi decoders, the authors study VLSI decompositions of deBruijn graphs. They obtain some strong necessary conditions for a graph to be a building block for a deBruijn graph, and some slightly more restrictive sufficient conditions which allow the construction of some efficient building blocks for deBruijn graphs.
Additional Information
© 1992 IEEE. The research described in this paper was partially carried out at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration. Tsz-Mei Ko's contribution was also supported by National Security Agency Grant No. MDA904-90-H-1007. Robert McEliece's contribution was also supported by AFOSR grant 91-0037 and a grant from Pacific Bell.Attached Files
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Additional details
- Eprint ID
- 29881
- Resolver ID
- CaltechAUTHORS:20120328-130309049
- National Security Agency
- MDA904-90-H-1007
- Air Force Office of Scientific Research (AFOSR)
- 91-0037
- Pacific Bell
- Created
-
2012-04-17Created from EPrint's datestamp field
- Updated
-
2021-11-09Created from EPrint's last_modified field
- Other Numbering System Name
- INSPEC Accession Number
- Other Numbering System Identifier
- 4407484