Bit-width Optimization for Configurable DSP's by Multi-interval Analysis

Abstract

A new algorithm for bounding the bit-widths of the data registers of an acyclic data-flow graph is presented. The method, based on the propagation of two's complement fixed-point numerical ranges, can be applied to both linear and nonlinear time invariant flow graphs and is well suited to be implemented in Field Programmable Gate Arrays (FPGA's). Numerical values are represented by unions of intervals, allowing automatic monitoring of the growth of the number of bits needed to represent the integer and the fractional part of intermediate variables. Central to this method is the definition of a new interval arithmetic on fixed point multi-intervals. An application of the proposed algorithm to the problem of detecting two dimensional visual features in video images is presented.

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