Published September 2006
| public
Book Section - Chapter
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices
Abstract
We present a novel 3D crossbar for future Network-on-a-Chip implementations. We introduce a routing algorithm for the 3D crossbar circuit and detail two specific 3D crossbar topologies. We evaluate the defect tolerance of the 3D crossbar and quantify the number of extra layers required to support arbitrary permutations as a function of the defect rate. Further, we estimate the circuit performance and advantages of the 3D crossbar circuit based on post-silicon devices.
Additional Information
© 2006 IEEE. Issue Date: Sept. 2006. Date of Current Version: 16 April 2007. The authors are grateful to Shinichi YASUDA and Dr. Tetsufumi TANAMOTO, Corporate R&D Center, Toshiba Corp., and Dr. Bipul C Paul and Dr. Masaoki OKAJIMA, Toshiba America Research, Inc., for helpful comments.Additional details
- Eprint ID
- 24476
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- CaltechAUTHORS:20110720-093755059
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2011-07-21Created from EPrint's datestamp field
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2021-11-09Created from EPrint's last_modified field
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- Other Numbering System Identifier
- 9366008