Published 2010
| Published
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All-Digital CDR for High-Density, High-Speed I/O
- Creators
- Loh, Matthew
-
Emami-Neyestanak, Azita
Chicago
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Abstract
A novel all-digital CDR for source-synchronous links, and its implementation in 90nm CMOS, is presented. A phase alignment technique with ping-pong action between two clock phases is used. The system is implemented in static CMOS logic, occupies 0.234 mm^2 and dissipates 16.6 mW at 6 Gb/s, demonstrating BER < 10^(-13) with PRBS-7 input. The compactness and all-static-CMOS nature of the system make it suitable for use in high-speed I/Os requiring per-pin synchronization.
Additional Information
© 2010 IEEE. Issue Date: 16-18 June 2010. Date of Current Version: 02 September 2010.Attached Files
Published - Loh2010p132692010_Symposium_On_Vlsi_Circuits_Digest_Of_Technical_Papers.pdf
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Additional details
- Eprint ID
- 23146
- Resolver ID
- CaltechAUTHORS:20110329-081801877
- Created
-
2011-05-25Created from EPrint's datestamp field
- Updated
-
2023-03-15Created from EPrint's last_modified field
- Series Name
- Symposium on VLSI Circuits-Digest of Papers
- Other Numbering System Name
- INSPEC Accession Number
- Other Numbering System Identifier
- 11515693