Accelerating SPICE Model-Evaluation using FPGAs
- Creators
- Kapre, Nachiket
- DeHon, André
Abstract
Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SPICE model-evaluation. Model-evaluation is a key component of the SPICE circuit simulator and it is characterized by large irregular floating-point compute graphs. We show how to exploit the parallelism available in these graphs on single-FPGA designs with a low-overhead VLIW-scheduled architecture. Our architecture uses spatial floating-point operators coupled to local high-bandwidth memories and interconnected by a time-shared network. We retime operation inputs in the model-evaluation to allow independent scheduling of computation and communication. With this approach, we demonstrate speedups of 2–18× over a dual-core 3GHz Intel Xeon 5160 when using a Xilinx Virtex 5 LX330T for a variety of SPICE device models.
Additional Information
© 2009 IEEE.Attached Files
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Additional details
- Eprint ID
- 18195
- Resolver ID
- CaltechAUTHORS:20100507-150521265
- Created
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2010-05-16Created from EPrint's datestamp field
- Updated
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2021-11-08Created from EPrint's last_modified field