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Published April 25, 2001 | Submitted
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An Asynchronous Microprocessor in Gallium Arsenide

Abstract

In this paper, several techniques for designing asynchronous circuits in Gallium Arsenide are presented. Several new circuits were designed, to implement specific functions necessary to the design of a full microprocessor. A sense-amplifier, a completion tree, and a general circuit structure for operators specified by production rules are introduced. These circuit were used and tested in a variety of designs, including two asynchronous microprocessors and two asynchronous static RAM's. One of the microprocessor runs at over 100 MIPS with a power consumption of 2 Watts.

Additional Information

© California Institute of Technology. We are indebted to Marcel van der Goot for his help in generating high quality software support. Acknowledgment is due to Steve Burns and Pieter Hazewindus, for their participation in the original design, and many very useful comments and conversations, and H. Peter Hofstee for his collaboration in the design of asynchronous memories. Many thanks to Ray Milano of Vitesse Semiconductors, for invaluable help with the HGAAS technology, and to Cindy Hibbert and Metasoftware, for their help with Hspice. The research described in this paper was sponsored by the Defense Advanced Research Projects Agency, DARPA Order number 6202, and monitored by the Office of Naval Research under contract number N00014-87-K-0745.

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Submitted - CS_TR_93_38.pdf

Submitted - postscript.ps

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August 20, 2023
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