Submicron Systems Architecture Project : Semiannual Technical Report, 1 July 1992
Abstract
The Mosaic C is an experimental fine-grain multicomputer based on single-chip nodes. The Mosaic C chip includes 64KB of fast dynamic RAM, processor, packet interface, ROM for bootstrap and self-test, and a two-dimensional selftimed router. The chip architecture provides low-overhead and low-latency handling of message packets, and high memory and network bandwidth. Sixty-four Mosaic chips are packaged by tape-automated bonding (TAB) in an 8 x 8 array on circuit boards that can, in turn, be arrayed in two dimensions to build arbitrarily large machines. These 8 x 8 boards are now in prototype production under a subcontract with Hewlett-Packard. We are planning to construct a 16K-node Mosaic C system from 256 of these boards. The suite of Mosaic C hardware also includes host-interface boards and high-speed communication cables. The hardware developments and activities of the past eight months are described in section 2.1. The programming system that we are developing for the Mosaic C is based on the same message-passing, reactive-process, computational model that we have used with earlier multicomputers, but the model is implemented for the Mosaic in a way that supports finegrain concurrency. A process executes only in response to receiving a message, and may in execution send messages, create new processes, and modify its persistent variables before it either exits or becomes dormant in preparation for receiving another message. These computations are expressed in an object-oriented programming notation, a derivative of C++ called C+-. The computational model and the C+- programming notation are described in section 2.2. The Mosaic C runtime system, which is written in C+-, provides automatic process placement and highly distributed management of system resources. The Mosaic C runtime system is described in section 2.3.
Additional Information
© 1992 California Institute of Technology. Reporting Period: 1 November 1991 - 30 June 1992. The research described in this report was sponsored by the Defense Advanced Research Projects Agency and monitored by the Office of Naval Research.Attached Files
Published - CS_TR_92_17.pdf
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Additional details
- Eprint ID
- 26759
- Resolver ID
- CaltechCSTR:1992.cs-tr-92-17
- Defense Advanced Research Projects Agency (DARPA)
- Office of Naval Research (ONR)
- Created
-
2001-04-25Created from EPrint's datestamp field
- Updated
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2023-08-08Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports
- Series Name
- Computer Science Technical Reports
- Series Volume or Issue Number
- 92-17