Welcome to the new version of CaltechAUTHORS. Login is currently restricted to library staff. If you notice any issues, please email coda@library.caltech.edu
Published July 25, 2002 | Accepted Version
Report Open

HEX: A Hierarchical Circuit Extractor

Oyang, Yen-Jen

Abstract

This report describes the algorithm, implementation, and performance of a hierarchical circuit extractor, HEX, for Metal-Oxide Semiconductor(M0S) layout designs at Caltech. The input to HEX is a layout design in Caltech intermediate Form(CIF), a hierarchical layout description language, and the output is a hierarchical netlist describing the circuit. HEX avoids redundant work by finding out the repetitive cells in the input CIF file. To handle overlapping instances, HEX modifies the hierarchy in the CIF file to generate a new one without overlapping instances. HEX then traverses the resulting hierarchical structure, calls a flat extractor to extract leaf cells and composes cells bottom up to get the circuit information of the whole chip.

Attached Files

Accepted Version - 5139_TR_84.pdf

Accepted Version - 5139_TR_84.ps

Files

5139_TR_84.pdf
Files (7.3 MB)
Name Size Download all
md5:d63d348b32a75602ad004fdf4b3a4048
2.9 MB Download
md5:d5f13910e0ffb8ad44a59bad9b87197c
4.4 MB Preview Download

Additional details

Created:
August 19, 2023
Modified:
December 22, 2023