Welcome to the new version of CaltechAUTHORS. Login is currently restricted to library staff. If you notice any issues, please email coda@library.caltech.edu
Published January 1, 1983 | public
Report Open

Automated Performance Optimization of Custom Integrated Circuits

Abstract

The complexity of integrated circuits requires a hierarchical design methodology that allows the user to divide the problem into pieces, design each piece independently, and assemble the pieces into the complete system. The design herarchy brings out composition problems, problems that are a property of the assembly as a whole, not of one single instance in the hierarchy. Recent research has produced tools that automate part of the composition task - the logical connection of the pieces. However, these tools do not ensure that signals driven over these connections will be driven sufficiently to give reasonable cycle speed of the resulting chips. It is easily possible to specify an assembly in which a small-sized gate is required to drive an enormous load. Parasitic capacitance of the wiring made automatically by the logical connection tool can be the dominant source of delay, so assembly tools can actually worsen the performance of the circuit and hide this fact from the designer. When required to make large circuits, automated layout tools such as PLA generators can blindly make layouts that give abysmally poor performance. Here again, the delay is in a part of circuit that the designer did not specify, so it is hidden. Finding and correcting these problems is a difficult and time-consuming task in integrated circuit design, and one that consumes vastly more people's time and computer time than the simple assembly of the chip.

Files

5073_TR_83.pdf
Files (23.0 MB)
Name Size Download all
md5:2e3b2e4c3d52773c33ac72f5f74df5b9
10.9 MB Preview Download
md5:fe36eeedbad7a3b6a7926572277945b1
12.1 MB Download

Additional details

Created:
August 19, 2023
Modified:
December 22, 2023