PLA Design in NAND Structure

Abstract

A NAND (serial gating) structure PLA of the MOS poly-silicon gate process has been developed for high density and medium fast speed VLSI application. Dynamic clocking is used for minimum power dissipation and elimination of the ratio problem associated with static NAND gate. Ion-implantation for memory cell programming and the elimination of contact in the memory area drastically reduces the cell size, and reliability is improved . A simple but effective self-timed clocking scheme is employed for better operating margins against process variations; the overhead chip area for the clock generation is sufficiently small. The advantages of allowing metal signal and power lines to cross the PLA memory area is discussed. Some measured data from a 3.5μm NMOS Si-gate process with regard to gate height and transistor sizes are also described.