Seven strategies for tolerating highly defective fabrication
- Creators
- DeHon, André
- Naeimi, Helia
Abstract
In this article we present an architecture that supports fine-grained sparing and resource matching. The base logic structure is a set of interconnected PLAs. The PLAs and their interconnections consist of large arrays of interchangeable nanowires, which serve as programmable product and sum terms and as programmable interconnect links. Each nanowire can have several defective programmable junctions. We can test nanowires for functionality and use only the subset that provides appropriate conductivity and electrical characteristics. We then perform a matching between nanowire junction programmability and application logic needs to use almost all the nanowires even though most of them have defective junctions. We employ seven high-level strategies to achieve this level of defect tolerance.
Additional Information
© Copyright 2005 IEEE. Reprinted with permission. We thank the Defense Advanced Research Projects Agency for supporting this research under Office of Naval Research contract N00014-04-1-0591. This material is based on work supported by the Department of the Navy, Office of Naval Research. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the Office of Naval Research.Files
Name | Size | Download all |
---|---|---|
md5:35dca87783c808eb11810be0e932645c
|
168.7 kB | Preview Download |
Additional details
- Eprint ID
- 5274
- Resolver ID
- CaltechAUTHORS:DEHieeedtc05
- Created
-
2006-10-06Created from EPrint's datestamp field
- Updated
-
2021-11-08Created from EPrint's last_modified field